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FDMF8700 Driver plus FET Multi-chip Module
March 2007
FDMF8700 Driver plus FET Multi-chip Module
Benefits
Fully optimized system efficiency. Higher efficiency levels are achievable compared with conventional discrete components. Space savings of up to 50% PCB versus discrete solutions. Higher frequency of operation. Simpler system design and board layout. Reduced time in component selection and optimization.
tm
General Description
The FDMF8700 is a fully optimized integrated 12V Driver plus MOSFET power stage solution for high current synchronous buck DC-DC applications. The device integrates a driver IC and two Power MOSFETs into a space saving, 8mm x 8mm, 56-pin Power88TM package. Fairchild Semiconductor's integrated approach optimizes the complete switching power stage with regards to driver to FET dynamic performance, system inductance and overall solution ON resistance. Package parasitics and problematical layouts associated with conventional discrete solutions are greatly reduced. This integrated approach results in significant board space saving, therefore maximizing footprint power density. This solution is based on the IntelTM DrMOS specification.
Features
12V typical Input Voltage Output current up to 30A 500KHz switching frequency capable Internal adaptive gate drive Integrated bootstrap diode Peak Efficiency >90% Under-voltage Lockout Output disable for lost phase shutdown Low profile SMD package RoHS Compliant
Applications
Desktop and server VR11.x V-core and non V-core buck converters. CPU/GPU power train in game consoles and high end desktop systems. High-current DC-DC Point of Load (POL) converters Networking and telecom microprocessor voltage regulators Small form factor voltage regulator modules
Powertrain Application Circuit
12V CVCC
VCIN DISB PWM Input DISB
VIN BOOT CBOOT
PWM CGND
VSWH PGND COUT
OUTPUT
Figure 1. Powertrain Application Circuit
Ordering Information
Current Rating Max [A] 30 Input Voltage Typical [V] 12 1 Frequency Max [KHz] 500 Device Marking FDMF8700
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Part FDMF8700
(c)2007 Fairchild Semiconductor Corporation
FDMF8700 Rev. C3
FDMF8700 Driver plus FET Multi- chip Module
Functional Block Diagram
BOOT VCIN HDRV VIN
DISB PWM
2.2
1.2 VSWH
1.2 VCIN
CGND
LDRV
PGND
Figure 2. Functional Block Diagram
Pin Configuration
CGND NC NC VCIN BOOT CGND VSWH VIN VIN TEST PAD1 VIN VIN VIN VIN 1 PWM 56 DISB NC NC NC CGND VSWH VSWH VSWH VSWH VSWH VSWH VSWH VSWH 43 14 15 VIN VIN VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND PGND 28 PGND 29 (CGND) (VIN) (VSWH) 42
Figure 3. Power88 56L Bottom View
VSWH VSWH VSWH TEST PAD2 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND 2
FDMF8700 Rev. C3
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FDMF8700 Driver plus FET Multi- chip Module
Pin Description
Pin
1,6,51 2,3,52,53,54 4 5 7,21,40-50 8,9,11-20 10 22-38 39 55 56
Name
CGND NC VCIN BOOT VSWH VIN TEST PAD 1 PGND TEST PAD 2 DISB PWM IC Ground. Ground return for driver IC. No connect
Function
IC Supply. +12V chip bias power. Bypass with a 1F ceramic capacitor. Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor. Switch Node Input. SW Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. Power Input. Output stage supply voltage. For manufacturing test only. HDRV pin. This pin must be floated. Must not be connected to any pin. Power ground. Output stage ground. Source pin of low side MOSFET(s). For manufacturing test only. LDRV pin. This pin must be floated. Must not be connected to any pin. Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low). PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
Absolute Maximum Rating
Parameter
VCIN to PGND VIN to PGND PWM, DSIB to GND VSWH to PGND BOOT to VSWH BOOT to PGND IO(AV) IO(PK) RJPCB PD Continuous Transient (t = 100ns, fsw = 500KHz) VIN = 12V, VO = 1.3V, fsw = 500KHz, TPCB = 100C VIN = 12V, tPULSE = 10s Junction to PCB Thermal Resistance (note 1) TPCB = 100C (note 1) -55 Continuous Transient (t = 100ns, fsw = 500KHz)
Min.
-0.5 -0.5 -0.3 -1 -5 -0.3 -0.3 -0.3
Max.
15 15 5.5 15 25 15 30 33 30 65 5.5 9.1 150
Units
V V V V V V V V A A C/W W C
Operating and Storage Junction Temperature Range
Recommended Operating Range
Parameter
VCIN VIN Control Circuit Supply Voltage Output Stage Supply Voltage
Min.
6.4 6.4
Typ.
12 12
Max.
13.5 14
Units
V V
Electrical Characteristics
VIN = 12V, TA = 25C unless otherwise noted.
Parameter
Control Circuit Supply Current Undervoltage lockout threshold PWM Input High Voltage
Symbol
ICIN VTH(UVLO)(2) VIH(PWM)
Conditions
fSW = 0Hz, VDISB = 0V fSW = 500KHz, VDISB = 5V Turn-on Turn-off
Min.
Typ.
3.5 18 6 5.25
Max.
8
Units
mA V V V
3.5
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FDMF8700 Driver plus FET Multi- chip Module
Electrical Characteristics
VIN = 12V, TA = 25C unless otherwise noted.
Parameter
PWM Input Low Voltage PWM Input Current Output Disable Input High Voltage Output Disable Input Low Voltage Output Disable Input Current Output Stage Leakage Current
Symbol
VIL(PWM) IPWM VIH(DISB) VIL(DISB) IDISB IIN_LEAKAGE tPDL(LDRV)(3) tPDL(HDRV)(3) tPDH(LDRV)(3) tPDH(HDRV)(3)
Conditions
Min.
-1 2.5
Typ.
Max.
0.8 1 0.8
Units
V A V V A A ns ns ns ns
-1 VDISB = 0V VIN = 12V, VOUT = 1.3V, fsw = 500KHz, IO = 30A 250 48 37 34 51
1
Propagation Delay
Note 1: Package power dissipation based on 4 layer, 2 square inch, 2 oz. copper pad. RJPCB is the steady state junction to PCB thermal resistance with PCB temperature referenced at VSWH pin. Note 2: When combined with controller, driver UVLO must be less than that of controller. Note 3: tPDL(LDRV/HRDV) refers to HIGH-to-LOW transition, tPDH(LDRV/HDRV) refers to LOW-to-HIGH transition.
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FDMF8700 Driver plus FET Multi-chip Module
Typical Characteristics
35 30
10 VIN = 12V VOUT = 1.3V L = 0.68uH
8
25
15 10 5 0 0 25 50 75 100 PCB Temperature, oC 125 150
PLOSS, W
ILOAD, A
20
6
fSW = 500KHz
4 fSW = 300KHz 2
VIN = 12V VOUT = 1.3V fSW = 500KHz L = 0.68uH
0 0 5 10 15 ILOAD, A 20 25 30
Figure 4. Safe Operating Area vs. PCB Temperature
Figure 5. Module Power Loss vs. Output Current (VO measured at VSWH pin)
1.20 1.15 PLOSS (NORMALIZED) 1.10 1.05 1.00 0.95 0.90
VIN = 12V VOUT = 1.3V IOUT = 30A L = 0.68uH
PLOSS (NORMALIZED)
1.3
1.2
1.1
1.0
VOUT = 1.3V IOUT = 30A L = 0.68uH fSW = 300KHz
6 7 8 9 10 11 12 13 14 15
0.9
200 250 300 350 400 450 500 Switching Frequency, KHz
Input Voltage, V
Figure 6. Power Loss vs. Switching Frequency
Figure 7. Power Loss vs. Input Voltage
1.10 1.08 1.05 1.03 1.00 0.98 0.95 7 8 9 10 11 12 13 Driver Supply Voltage, V
1.6
PLOSS (NORMALIZED)
PLOSS (NORMALIZED)
1.4
VIN = 12V IOUT = 30A L = 0.68uH fSW = 300KHz
1.2
VIN = 12V VOUT = 1.3V IOUT = 30A L = 0.68uH fSW = 300KHz
1.0
0.8 0.8 1.2 1.6 2.0 Output Voltage, V 2.4 2.8 3.2
Figure 8. Power Loss vs. Supply Voltage
Figure 9. Power Loss vs. Output Voltage
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FDMF8700 Driver plus FET Multi-chip Module
1.10
4.4 4.2
PLOSS (NORMALIZED)
1.05
4.0
Supply Current, mA
3.8 3.6 3.4 3.2 3.0 2.8 PWM=DISB=0V PWM=DISB=5V
1.00
0.95
VIN = 12V VOUT = 1.3V IOUT = 30A fSW = 300KHz
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.90 Output Inductance, uH
6
7
8
9
10
11
12
13
14
15
Supply Voltage, V
Figure 10. Power Loss vs. Output Inductance
Figure 11. Supply Current vs. Supply Voltage
3.3
20 VCIN = 12V VCIN = 12V IQ 16 Supply Current, mA
50
o
3.2 Supply Current, mA
IQ_OFF
3.1
12
3.0
8
2.9
4
2.8 -50 -25 0 25 75 100 125 150 Temperature, C
0 0 100 200 300 Frequency, kHz 400 500
Figure 12. Supply Current vs. Temperature
Figure 13. Supply Current vs. Frequency
2.0 VIH 1.9 DISB Threshold Voltage, V DISB Threshold Voltage, V 1.8 1.7 1.6 VIL 1.5 1.4 6 7 8 9 10 11 12 13 14 15 Driver Supply Voltage, V
2.0 VCIN = 12V 1.9 VIH 1.8 1.7 1.6 VIL 1.5 1.4 -50 -25 0 25 50 75 100 125 150 Temperature, oC
Figure 14. DISB Threshold Voltage vs. Driver Supply Voltage
Figure 15. DISB Threshold Voltage vs. Temperature
FDMF8700 Rev. C3
6
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FDMF8700 Driver plus FET Multi-chip Module
3.0 VIH 2.7 PWM Threshold Voltage, V 2.4 2.1 1.8 1.5 1.2 6 7 8 9 10 11 12 13 14 15 Driver Supply Voltage, V VIL PWM Threshold Voltage, V
3.0 VCIN = 12V 2.7 2.4 2.1 1.8 1.5 1.2 -50 -25 0 25 50 75 100 125 150 Temperature, oC VIL VIH
Figure 16. PWM Threshold Voltage vs. Driver Supply Voltage
Figure 17. PWM Threshold Voltage vs. Temperature
-13
36 35 34 33 32 31 30 0 100 200 300 400 500 0 100 200 300 400 500
Transient Duration, nsec
-11 VBOOT - GND, V
-9
VSW, V
-7
-5
-3
Transient Duration, nsec
Figure 18. VSWH vs. Transient Duration
Figure 19. Boot to Ground Voltage vs. Transient Duration
PWM HDRV
PWM HDRV
LDRV
VSWH
VIN = 12V VCIN = 12V VOUT = 1.3V fsw = 300KHz IOUT = 0A
LDRV
VSWH
VIN = 12V VCIN = 12V VOUT = 1.3V fsw = 300KHz IOUT = 30A
Figure 20. Switching Waveform at Iout = 0A
Figure 21. Switching Waveform at Iout = 30A
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FDMF8700 Driver plus FET Multi-chip Module
PWM HDRV VIN = 12V VCIN = 12V VOUT = 1.3V fsw = 300KHz IOUT = 30A
PWM HDRV
LDRV
LDRV
VSWH
VSWH
VIN = 12V VCIN = 12V VOUT = 1.3V fsw = 300KHz IOUT = 30A
Figure 22. Switching Waveform (Rising edge)
Figure 23. Switching Waveform (Falling Edge)
FDMF8700 Rev. C3
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FDMF8700 Driver plus FET Multi-chip Module
Description of Operation
Circuit Description
The FDMF8700 is a driver plus FET module optimized for synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 500KHz.
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to Figure 24 and 25 for the relevant timing waveforms. To prevent overlap during the low-to-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay (tPDL(LDRV)). Once the LDRV pin is discharged below ~1.2V, Q1 begins to turn ON after adaptive delay tPDH(HDRV). To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the SW pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (tPDL(HDRV)). Once the VSWH pin falls below ~2.2V, Q2 begins to turn ON after adaptive delay tpdh(LDRV). Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven ON after tPDH(LDRV), regardless of SW state. This function is implemented to ensure CBOOT is recharged each switching cycle, particularly for cases where the power convertor is sinking current and SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay tPDH(HDRV) is longer than tPDH(LDRV).
Low-Side Driver
The low-side driver (LDRV) is designed to drive a ground referenced low RDS(ON) N-channel MOSFET. The bias for LDRV is internally connected between VCIN and CGND. When the driver is enabled, the driver's output is 180 out of phase with the PWM input. When the driver is disabled (DISB = 0V), LDRV is held low.
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal diode and external bootstrap capacitor (CBOOT). During start-up, VSWH is held at PGND, allowing CBOOT to charge to VCIN through the internal diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to VSWH. CBOOT is then recharged to VCIN when VSWH falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
DISB
VIH(DISB) VIL(DISB) tPDL(DISB) tPDH(DISB)
LDRV / HDRV Figure 24. Output Disable Timing VIH(PWM) PWM tPDL(LDRV) LDRV 1.2V tPDH(HDRV)
VIL(PWM)
HDRV-SW
tPDL(HDRV) tPDH(LDRV)
SW 2.2V Figure 25. Adaptive Gate Drive Timing
FDMF8700 Rev. C3
9
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FDMF8700 Driver plus FET Multi-chip Module
Typical Application
VCIN 12V VIN 12V VCIN DISB PWM BOOT VIN FDMF8700 VSWH CGND PGND HDRV LDRV
VCC PWM1 PWM PWM2 Controller PWM3 PWM4 LDRV EN
VCIN DISB BOOT PWM VIN FDMF8700 VSWH CGND PGND HDRV LDRV
VCIN DISB PWM BOOT VIN FDMF8700 VSWH CGND PGND HDRV LDRV
VOUT
Signal GND
Power GND
VCIN DISB PWM BOOT VIN FDMF8700 VSWH CGND PGND HDRV LDRV Figure 26. Typical Application
Application Information Supply Capacitor Selection
For the supply input (VCIN) of the FDMF8700, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1F, X7R or X5R capacitor. Keep this capacitor close to the FDMF8700 VCIN and CGND pins. The average diode forward current, IF(AVG), can be estimated by:
IF(AVG) = QG x fSW
(2)
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBOOT) and the internal diode, as shown in Figure 26. Selection of these components should be done after the high-side MOSFET has been chosen. The required capacitance is determined using the following equation:
where fSW is the switching frequency of the controller. The peak surge current rating of the internal diode should be checked in-circuit, since this is dependent on the equivalent impedance of the entire bootstrap circuit, including the PCB traces. For applications requiring higher IF, an external diode may be used in parallel to the internal diode.
CBOOT >=
QG VBOOT
(1)
where QG is the total gate charge of the high-side MOSFET, and VBOOT is the voltage droop allowed on the high-side MOSFET drive. For example, the QG of the internal high-side MOSFET is about 21nC @ 12VGS. For an allowed droop of ~300mV, the required bootstrap capacitance is > 100nF. A good quality ceramic capacitor must be used.
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FDMF8700 Driver plus FET Multi-chip Module
Module Power Loss Measurement and Calculation
Refer to Figure 27 for module power loss testing method. Power loss calculation are as follows: (a) PIN (b) POUT (c) PLOSS = (VIN x IIN) + (VCIN x ICIN) (W) = VO x IOUT (W) = PIN - POUT (W)
1. Input bypass capacitors should be close to VIN and GND pin of FDMF8700 to help reduce input current ripple component induced by switching operation. 2. It is critical that the VSWH copper has minimum area for lower switching noise emission. VSWH copper trace should also be wide enough for high current flow. Other signal routing path, such as PWM IN and BOOT signal, should be considered with care to avoid noise pickup from VSWH copper area. 3. Output inductor location should be as close as possible to the FDMF8700 for lower power loss due to copper trace. 4. Place ceramic bypass capacitor and boot capacitor as close to VCIN and BOOT pin of FDMF8700 in order to supply stable power. Routing width and length should also be considered. 5. Use multiple Vias on each copper area to interconnect each top, inner and bottom layer to help smooth current flow and heat conduction. Vias should be relatively large and of reasonable inductance.
PCB Layout Guideline
Figure 28. shows a proper layout example of FDMF8700 and critical parts. All of high current flow path, such as VIN, VSWH, VOUT and GND copper, should be short and wide for better and stable current flow, heat radiation and system performance. Following is a guideline which the PCB designer should consider: DISB PWM input
CBOOT
ICIN VCIN A CVCIN IIN VIN A CVIN VIN VCIN
PWM
DISB
BOOT L IOUT A V VO COUT VOUT
FDMF8700
VSWH
CGND
PGND
IC Ground
Power Ground
Figure 27. Power Loss Measurement Block Diagram
Figure 28. Typical PCB Layout Example (Top View)
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11
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FDMF8700 Driver plus FET Multi-chip Module
Dimensional Outline and Pad layout
(DATUM A)
Bayan Lepas FIZ 11900, Penang, Malaysia
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12
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FDMF8700 Driver plus FET Multi-chip Module
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx(R) Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM E2CMOSTM EcoSPARK(R) EnSignaTM FACT Quiet SeriesTM FACT(R) FAST(R) FASTr(R) FPSTM FRFET(R) GlobalOptoisolatorTM GTOTM HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANAR(R) PACMANTM POPTM Power220(R) Power247(R) PowerEdgeTM PowerSaverTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM SPM(R) SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 TCMTM The Power Franchise(R) TM TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM UHC(R) UniFETTM VCXTM WireTM
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I23
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
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